1. Field of Invention
The present invention relates to a method of fabricating a capacitor with high capacitance. More particularly, the present invention relates to a method of fabricating a capacitor with high capacitance by forming storage nodes with a gear toothed profile.
2. Description of Related Art
A dynamic random access (DRAM) is an integrated circuit (IC) device that has been used broadly in every kind of field, and especially in the electronics industry. With the steady improvement in IC fabrication, a DRAM with higher capacitance is in great demand. People in the industry are devoted to the study of how to fabricate a capacitor with high capacitance while dimensions of devices are reduced.
A stacked capacitor (STC) structure, one kind of a DRAM capacitor structure, is used to satisfy the requirement of reducing dimensions of IC devices. But some difficulties gradually appear while increasing capacitance of a STC. A DRAM memory usually includes a STC structure and a transfer gate transistor above the STC structure. The STC is connected with the source of the transfer gate transistor. However, the dimension of the STC structure is restricted by the gradually reduced dimension of the transfer gate transistor. The STC includes two electrodes separated by a dielectric layer. The thickness of the dielectric layer is necessarily reduced or the area of the capacitor is increased in order to increase the capacitance of the STC structure. However, the amount by which the thickness of the dielectric layer can be reduced is limited by considerations of device reliability.